A typical gallium nitride (GaN) device (e.g., a GaN transistor) is fabricated by depositing a nucleation layer over a base substrate, and subsequently depositing a buffer layer over the nucleation layer, where the nucleation layer functions to initiate epitaxial growth of the buffer layer. After deposition of the nucleation and buffer layers, additional GaN material, other semiconductor layers, and other structures (e.g., gate, drain, and source contacts) are formed over the buffer layer to complete the device.
A memory effect referred to as “drain lag” is a significant issue in GaN semiconductor devices. Drain lag is a trapping phenomenon that originates in inherent material characteristics such as lattice mismatches at the origin of dislocations. More specifically, drain lag is at least partially caused by traps in the epitaxial material between the channel and the base substrate, where the epitaxial material includes the nucleation and buffer layers. Ideally, the nucleation and buffer layers would be electrically inactive. In practice, however, these layers may contribute significant and undesirable leakage current and output conductance, thus decreasing the performance of the GaN device.